Typically, an electronic circuit or part of an electronic circuit (commonly called a VFI for “Voltage Frequency Island”), both designated by “circuit” below, are controlled so as to apply to them at each instant a voltage and a frequency within their operating domain and so as to limit the energy consumption while meeting performance constraints (number of operations per unit time). For this purpose, the controlled electronic circuit is associated with a “voltage actuator” and with a “frequency actuator” enabling the chosen voltage and frequency to be applied. These two actuators may themselves be controlled by an internal feedback control loop.
A voltage-frequency pair in the operating domain is commonly called an operating point.
In practice, it should be ensured that for the applied voltage, the applied frequency is not too high in order not to give rise to “timing faults”.
Numerous bibliographical references and patents set out what are referred to as “DVFS” approaches (DVFS standing for “Dynamic Voltage Frequency Scaling”) to control the voltage and the frequency.
In Published U.S. Pat. Application No. 2011/0083221 the voltage is increased in a first phase then a frequency change request is made in a second phase. The value of the voltage has a direct link with the value of the changed frequency. A sequence of voltage changes and a sequence of frequency changes may be applied. A voltage change indicator indicates the end of the preceding step. The transition to pass from a high voltage value to a low voltage value (and vice-versa) and/or from a high frequency value to a low frequency value (and vice-versa) is not controlled.
In the paper by Zhu et al. “Feedback EDF scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling” ACM SIGPLAN Notices, vol 40:7, pp. 212-222, 2005, the voltage is increased then subsequently the frequency. The case of the reduction in these parameters is not dealt with. At the time of modifying the voltage-frequency operating point (V, F), the voltage increases as a ramp function. The time necessary to attain the minimum voltage required for the application of the new desired frequency without any timing fault is then estimated. When this time has passed, the new frequency is applied. Frequency and voltage are thus controlled sequentially.
In the paper by Wu et al. “Formal online methods for voltage/frequency control in multiple clock domain microprocessors” ACM SIGARCH Computer Architecture News, vol 32:5, pp. 248-259, 2004, DVFS is dealt with in terms of a problem of adjusting the frequency to adapt to the variations in load. A “perfect” DVFS scheme enables the desired performance to be obtained, without needless consumption. A queue type model is used to model the frequency domain. The model used is non-linear: it is first of all linearized then a linear control law is implemented via hardware. This document specifies that the frequency and the associated voltage cannot be modified instantaneously. For the control, a control interval itself constituted by N sampling periods is used. The frequency is deduced based on the computation of the execution capability itself output from a standard digital PI (Proportional-Integral) controller. In practice, it is not the frequency dynamic that is controlled, but the execution capability dynamic. Lastly, no information is given as to the way to modify the voltage relative to the frequency or as to the transition between two operating points.
The document by Juang et al. “Distributed, Formal Energy Management of Chip Multiprocessors” ISLPED'05, 8-10 Août, 2005, San Diego, Calif., USA extends the approach in the document by Wu et al. to the case of a multi-processor system. A distributed control approach is implemented. Here too, no information as to the frequency and voltage transitions is given, nor as to the coupling of these parameters.
The paper by Choi et al., “Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol 24:1, 18-28, 2005, also presents a DVFS but without dealing with the question of the transition from one operating point to another.
In the paper by Lu et al., “Control-theoretic dynamic frequency and voltage scaling for multimedia workloads” Proc. of the international conference on compilers, architecture, and synthesis for embedded systems, pp. 156-163, 2002, concerning a multimedia application, the voltage V and the frequency F of a processor are adapted according to the frame throughput. In fact, control theory is used to adapt the frequency F while providing for the desired throughput (and thus the desired delay). In practice, a “frequency factor” comprised between 0 and 1, is adapted but the control is made on the average delay. No information is given as to the dynamic of the frequency transitions. It is only indicated that the frequency transition (induced by modifying the frequency factor) is short compared with the decoding time for a frame. Nothing is indicated as to the modifications to voltage nor as to the way in which voltage and frequency should be managed to avoid timing faults.
The paper by Herbert et al., “Variation-aware dynamic voltage/frequency scaling” IEEE 15th International Symposium on High Performance Computer Architecture (HPCA), 301-312, 2009 deals with DVFS (Dynamic Voltage and Frequency Scaling) but it does not refer to the transition problems which arise at the time of voltage and frequency modifications.
The inventors have found that in the prior art, the transition of a passage from one operating point to another was not optimally controlled.
In particular, the inventors have found that DVFS systems pass from one operating point to another sequentially by separately modifying voltage and frequency in order to avoid timing faults.
This sequential passage is illustrated by FIG. 1.
FIG. 1 illustrates a voltage-frequency operating domain by two orthogonal axes with the voltage V along the x-axis and the frequency along the y-axis. The operational (or operating) region (or domain) of the circuit considered is delimited by the x-axis (given that the frequency is a positive quantity), a vertical first boundary (Boundary 1) representing the maximum voltage the voltage-frequency operating domain considered of the circuit can bear and a second boundary (Boundary 2) representing for each voltage value allowable by the circuit, the maximum authorized frequency (to avoid timing faults).
FIG. 1 illustrates the passage from a first operating point (V1, F1) to a second operating point (V2, F2). According to the prior art, this passage is made in two phases passing via an intermediate operating point (V2, F1). This passage in two phases avoids going out of the operational region.
Nevertheless, during the course of the transition (i.e. the passage from point (V1, F1) to point (V2, F2)), the dynamic consumption of the circuit is not optimum.
To be precise, the dynamic power Pdyn is proportional to the frequency F and has a quadratic relationship with voltage V (Pdyn∝FV2). However, throughout the transition schematized by arrows T1 and T2, the frequency could be higher. Admittedly, more power would be consumed but the performance of the circuit would be improved (in terms of the number of operations per unit time).
The inventors have thus exposed a need to improve the voltage-frequency control of electronic circuits.